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Altera_Forum's avatar
Altera_Forum
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13 years ago

QSYS ignores readdatavalid signal

Hi, I am currently working on an Avalon memory master that requires the readdatavalid signal to properly function. I set up the signal in QSYS but when I observed the Signaltap output for a memory re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Sorry I should have re-read my answer... I meant only if the parameter is not 0. When 0 it basically means there is no pipelining and the read data valid signal isn't needed. Try to set it to another value (ideally to the highest number of transactions you plan to have before getting a read value back) and see if the signal becomes valid.