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Altera_Forum's avatar
Altera_Forum
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13 years ago

QSYS ignores readdatavalid signal

Hi, I am currently working on an Avalon memory master that requires the readdatavalid signal to properly function. I set up the signal in QSYS but when I observed the Signaltap output for a memory re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Did you declare that the avalon master would use pipelining? It is possible that QSys would only generate the logic behind the read data valid signal when the "Maximum pending read transactions" parameter is 0.