Forum Discussion

Occasional Contributor

1 year ago

qsys-generate does not create vcs simulation support directory

I have created two IP files (signaltap) for two different devices: A5EC008BM16AE6S and 10CX220YF780E5G. If I create the simulation files for 10CX220YF780E5G using qsys-generate I get both a vcs and...

qsys-generate-test.tgz3 KB

Simulation

RichardT_altera

Super Contributor

1 year ago

Beginning with Quartus Prime software version 24.2, the VCS 2-step flow is not supported for Agilex™ 5 devices. Agilex™ 5 devices support VCS only using the VCS MX 3-step flow.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683870/24-3/vcs-simulation-setup-script-example.html

Please checkout this KDB below:

https://www.intel.com/content/www/us/en/support/programmable/articles/000098428.html

Regards,

Richard Tan

zutalors
New Contributor
1 year ago
Thank you Richard,
Is vcs supported if using a three step compilation and Verilog/SystemVerilog IP or is a Synopsys MX license required due to some Altera IP being provided in VHDL only?

Will this transition also will be applied to Agilex7 in the near future?

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qsys-generate does not create vcs simulation support directory

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