QSYS flattens our design hierarchy

Hi all,

We are migrating from Xilinx to Altera and so far everything is running ok. As an alternative to Xilinx IP-integrator, we've now moved to QSYS. Here we get problems.

First issue: It seems QSYS copies all files from our IP to one single directory! (/synthesis/submodules) Doing this, it overwrites files with the same name, which is a big problem.

We have a large IP database, build up over many years. Each IP block contains a version of common packages (i.e. common_pkg.vhd). But due to new insights or upgrades, the contents of these files can differ between IP blocks. -We do not want versioning in the file name (e.g. common_pkg_v1_0.vhd), we want a specific version within a specific IP block directory-

Second issue: even if the file name would be different, it seems QSYS compiles everything into one VHDL library! This gives the same problem again: packages or components with the same name are overwritten. It might also all our library references in the code to malfunction, but we weren't able to check that yet.

So two questions:

- How do I specify the directory QSYS should copy the files in? (e.g. /synthesis/submodules/[IPmodule]/)

- How do I specify the library the IP block files should be compiled in? (i.e. not the default)

In Xilinx IPI this is quite easy. But after an extensive search I've found no way to do it in QSYS. I am quite worried about the information I found here: http://www.alterawiki.com/wiki/new_qsys_issues

If these things are not possible, I would be stumped. It would make QSYS unusable for us :/