QSYS flattens our design hierarchy

Thank you Dave, I will try your suggestion.

Project management has accepted the hard paths in the qip-file for now, so we have something we can work with. However, I do not consider this case closed until Altera Qsys allows library assignment per IP block.

This is so weird to me. VHDL libraries have been defined in the IEEE 1076-1987 VHDL standard already (section 11.2). Why is Altera still supporting them so badly after 28(!!) years?