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Altera_Forum
Honored Contributor
Honored ContributorQSYS flattens our design hierarchy
Hi all, We are migrating from Xilinx to Altera and so far everything is running ok. As an alternative to Xilinx IP-integrator, we've now moved to QSYS. Here we get problems. First issue: I...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Project management has accepted the hard paths in the qip-file for now, so we have something we can work with. --- Quote End --- Arguably they are not hard paths, since they are dynamically generated by the Tcl script :) --- Quote Start --- However, I do not consider this case closed until Altera Qsys allows library assignment per IP block. This is so weird to me. VHDL libraries have been defined in the IEEE 1076-1987 VHDL standard already (section 11.2). Why is Altera still supporting them so badly after 28(!!) years? --- Quote End --- I agree. Their VHDL support is terrible in multiple places, check out the comments at the end of the Avalon-MM BFM tutorial I wrote: https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_avalon_bfm_master.pdf https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_avalon_bfm_master.zip Cheers, Dave
