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Altera_Forum's avatar
Altera_Forum
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14 years ago

Qsys doesn't generate memory model

I have a hierarchical Qsys system containing a NIOSII, two DDR3 memory controllers and some video processing modules.

One of my subsystems is ddr3_system, which instantiates a DDR3 memory controller and the memory tester modules taken from the Qsys tutorial.

In my top level Qsys system I have two instances of ddr3_system.

Now, when I generate a testbench for ddr3_system, Qsys instantiates a DDR3 memory model (Altera DDR3 Memory Model for UniPHY), and connects it to the memory interface of the controller. But when I generate a testbench for my top level system, Qsys doesn't instantiate a DDR3 memory model - instead, it instantiates an "Altera Conduit BFM".

Does anyone have a suggestion on how I can get Qsys to instantiate the memory model when I generate my top level system?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If all you need is a model of the DDR3 memory, the memory makers often have that. Micron for example has verilog models for many DIMMs and individual SDRAMs. Just go to their webpage, select the correct product type, etc, pick something close to what you configured your IP for (or download the model and configure the IP to what the Micron spec says) and then run it. This works fine for me.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hmmm that sounds like a bug. The memory model is what is called a "companion BFM" meaning that Qsys is supposed to automatically bolt it up to the PHY interface for you. Have you tried this with a single SDRAM controller at the top? I'm suspecting it is caused by there being two of them but I have no idea why that would be a problem.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I haven't tried with only one controller. You could be right that the fact that I use two controllers confuse Qsys. Or it could be that Qsys is confused because the controllers are not on the top level.

    Anyway, the work-around I use at the moment is the following:

    - Open the top level Qsys system

    - In the Generation tab, select "Create testbench Qsys system: Standard, BFMs for standard Avalog interfaces"

    - Press generate

    - Open the generated Qsys testbench system

    - Delete the Conduit BFMs connected to the memory interfaces

    - Insert 2x of Altera DDR3 Memory Model for UniPHY, and connect them to the memory interfaces

    - And finally, generate simulation model for the testbench Qsys system