Qsys doesn't generate memory model

I haven't tried with only one controller. You could be right that the fact that I use two controllers confuse Qsys. Or it could be that Qsys is confused because the controllers are not on the top level.

Anyway, the work-around I use at the moment is the following:

- Open the top level Qsys system

- In the Generation tab, select "Create testbench Qsys system: Standard, BFMs for standard Avalog interfaces"

- Press generate

- Open the generated Qsys testbench system

- Delete the Conduit BFMs connected to the memory interfaces

- Insert 2x of Altera DDR3 Memory Model for UniPHY, and connect them to the memory interfaces

- And finally, generate simulation model for the testbench Qsys system