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Altera_Forum's avatar
Altera_Forum
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8 years ago

Qsys DDR4 Design Fails on Fit

I'm new to Altera & Quartus,

I had just learned about Qsys and have attempted to use it to compile a design implementing a DDR4 external interface on an Arria 10. I'm not trying to make a working design, just trying to compile this test design (which in Qsys only includes the external clock, an Altera IOPLL, and the Arria 10 External Interface). The error is caused by includeding this PLL (shown below).

Without the PLL in the Qsys design the compilation works, the external clock is 100MHz though so it needs to be multiplied to match the reference clock expected by the memory controler 266.667MHz.

Error (18101): An external memory interface or PHYLite IP core reference clock fed by a cascaded PLL. Connect the external memory interface or PHYLite IP core reference clock to an input buffer.

Info (18102): Upstream PLL: test_external_memory_altera_iopll_170_trjuqni:iopll_0|altera_iopll:altera_iopll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst

Info (18103): Downstream PLL: test_external_memory_altera_emif_170_tof6tea:emif_0|test_external_memory_altera_emif_arch_nf_170_6nk2gbq:arch|test_external_memory_altera_emif_arch_nf_170_6nk2gbq_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst

https://alteraforum.com/forum/attachment.php?attachmentid=13909&stc=1

https://alteraforum.com/forum/attachment.php?attachmentid=13910&stc=1

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    That message is telling you to connect the clock input. The memory controller is inside the I/O column of the device so the reference clock needs to be pinned out to the appropriate pin for the instance you are attempting to instantiate. The memory controller user guide probably has a step by step set of instructions to follow, I recommend taking a look at it. Past memory controllers documented the flow when using Qsys as well.

  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    Having struggled through this exact problem, the answer is the EMIF pll_ref_clk can't be hooked up to an internal PLL pin. It must be connected to an external pin. The allowed frequency of an oscillator attached to this pin is set via a drop down box in the EMIF IP application. There is a check box, defaulted to being checked, that will select the highest clock frequency in the list to reduce jitter. In my design I had two EMIFs. The fitter would not successfully fit the two EMIFs if they shared the same external clock pin.