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Altera_Forum
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8 years ago

Qsys DDR4 Design Fails on Fit

I'm new to Altera & Quartus, I had just learned about Qsys and have attempted to use it to compile a design implementing a DDR4 external interface on an Arria 10. I'm not trying to make a worki...
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Altera_Forum
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8 years ago

That message is telling you to connect the clock input. The memory controller is inside the I/O column of the device so the reference clock needs to be pinned out to the appropriate pin for the instance you are attempting to instantiate. The memory controller user guide probably has a step by step set of instructions to follow, I recommend taking a look at it. Past memory controllers documented the flow when using Qsys as well.