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Honored Contributor
Honored ContributorQsys DDR4 Design Fails on Fit
I'm new to Altera & Quartus, I had just learned about Qsys and have attempted to use it to compile a design implementing a DDR4 external interface on an Arria 10. I'm not trying to make a worki...
Altera_ForumHonored Contributor
Honored ContributorHaving struggled through this exact problem, the answer is the EMIF pll_ref_clk can't be hooked up to an internal PLL pin. It must be connected to an external pin. The allowed frequency of an oscillator attached to this pin is set via a drop down box in the EMIF IP application. There is a check box, defaulted to being checked, that will select the highest clock frequency in the list to reduce jitter. In my design I had two EMIFs. The fitter would not successfully fit the two EMIFs if they shared the same external clock pin.
