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Altera_Forum's avatar
Altera_Forum
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14 years ago

Qsys component creation

Hello,

I am migrating an existing project from SOPC to QSYS and I have some problems with the component editor of QSYS.

In my old SOPC system, my custom components where defined as .ptf files. So I need to generate .tcl files instead in order to be able to use them in QSYS.

What I did is the following:

1/ open the component editor in QSYS

2/ HDL files tab: add the .hdl file of my component in order to have all the required signals in the signals tab

3/ remove the .hdl file

4/ I have then the signals that you see on the attached picture "SignalsPicture.jpg"

5/ HDL Parameters tab: the problem now is that I have "conduit" signals which I did not expect attached to my bloc when I take a look at the preview of the GUI (see "PreviewGUI.jpg").

Is there a way to remove those signals?

I also noticed that these ones are not present when I generate the component without removing the .hdl file in the "HDL files" tab.

How is that so?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    i don't quite understand why you are removing the HDL files, but have you tried the Remove Interfaces With No Signals button on the Interfaces tab?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    but have you tried the Remove Interfaces With No Signals button on the Interfaces tab

    --- Quote End ---

    yes, but these signals do not appear in the "interfaces tab", only when the component is generated.

    I really do not understand from where these clk_reset1, avalon_slave_01 and avalon_slave_0_irq1 come from.

    It is strange because I can't see these signal in the .tcl file. 

    # TCL File Generated by Component Editor 11.0#  Wed Jun 08 19:14:38 CEST 2011#  DO NOT MODIFY
#  +-----------------------------------#  | #  | ccd_ctrl "ccd_ctrl" v1.0.1#  | null 2011.06.08.19:14:38#  | #  | #  | #  | #  +-----------------------------------
#  +-----------------------------------#  | request TCL package from ACDS 11.0#  | 
package require -exact sopc 11.0#  | #  +-----------------------------------
#  +-----------------------------------#  | module ccd_ctrl#  | 
set_module_property NAME ccd_ctrl
set_module_property VERSION 1.0.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Unknown Group"
set_module_property DISPLAY_NAME ccd_ctrl
set_module_property TOP_LEVEL_HDL_FILE ""
set_module_property TOP_LEVEL_HDL_MODULE ""
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE false
set_module_property ANALYZE_HDL TRUE
set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""
set_module_property FIX_110_VIP_PATH false#  | #  +-----------------------------------
#  +-----------------------------------#  | files#  | #  | #  +-----------------------------------
#  +-----------------------------------#  | parameters#  | #  | #  +-----------------------------------
#  +-----------------------------------#  | display items#  | #  | #  +-----------------------------------
#  +-----------------------------------#  | connection point clk#  | 
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true
add_interface_port clk clk clk Input 1#  | #  +-----------------------------------
#  +-----------------------------------#  | connection point clk_reset#  | 
add_interface clk_reset reset end
set_interface_property clk_reset associatedClock clk
set_interface_property clk_reset synchronousEdges DEASSERT
set_interface_property clk_reset ENABLED true
add_interface_port clk_reset reset reset Input 1#  | #  +-----------------------------------
#  +-----------------------------------#  | connection point avalon_slave_0#  | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clk
set_interface_property avalon_slave_0 associatedReset clk_reset
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 explicitAddressSpan 32
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 isMemoryDevice true
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitStates 1
set_interface_property avalon_slave_0 writeWaitTime 1
set_interface_property avalon_slave_0 ENABLED true
add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 read read Input 1
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 address address Input 3
add_interface_port avalon_slave_0 writedata writedata Input 32
add_interface_port avalon_slave_0 readdata readdata Output 32#  | #  +-----------------------------------
#  +-----------------------------------#  | connection point avalon_slave_0_irq#  | 
add_interface avalon_slave_0_irq interrupt end
set_interface_property avalon_slave_0_irq associatedAddressablePoint avalon_slave_0
set_interface_property avalon_slave_0_irq associatedClock clk
set_interface_property avalon_slave_0_irq associatedReset clk_reset
set_interface_property avalon_slave_0_irq ENABLED true
add_interface_port avalon_slave_0_irq irq irq Output 1#  | #  +-----------------------------------
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I haven't seen this happen before but you could try refreshing the component library to see if that helps.

    Also if you have a working component in SOPC Builder you shouldn't have to recreate the component in Qsys, it should migrate in most cases.

    If this continues please file a service request here so that Qsys engineering team can take a look and correct this: http://www.altera.com/mysupport
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Also if you have a working component in SOPC Builder you shouldn't have to recreate the component in Qsys, it should migrate in most cases

    --- Quote End ---

    All the components are .ptf files (classic components) which do not work with QSYS

    --- Quote Start ---

    you could try refreshing the component library to see if that helps

    --- Quote End ---

    In Qsys? You mean with F5?

    It did not help.

    --- Quote Start ---

    i don't quite understand why you are removing the HDL files

    --- Quote End ---

    To speed up the compilation process.