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Altera_Forum's avatar
Altera_Forum
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14 years ago

QSYS and symbols

I'm running into the most frustrating issue with qsys.. I hope I'm missing some simple thing.

The problem is I have a sysq-system and I use schematics as the top level so I create a symbol file of course from qsys and instantiate it at the top level.. Now, when I do some modification in the Qsys and regenerate and subsequently update the symbol then all pins get randomly changed to differnt locations in the symbol..

How can I fix this? It is most annoying to shuffle all pins again to the right pins. SOPC never did this before.

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I use schematic based top level design, but noticed something similar with Qsys. The order of the inputs and outputs in the top level module generated by Qsys seems to be random.

    Not nearly as big a problem for me of course, but I was in the habit of comparing the top level sopc builder module to my source to make sure I wasn't missing any connections. Not nearly as easy to do now.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes, as I have DDR2 and video inputs/outputs it becomes quite a task to reshuffle all pins to their correct location after any qsys mods..

    Altera, please fix this issue!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Unfortunately, not only that - seems that Qsys has a lot of schematic problems.

    First of all, there is no distinction between inputs and outputs anymore (?!?), unless you open up the symbol file (inputs are light blue, while outputs are purple). The "new and improved" interface has all the signals on one side, so it's pretty much impossible to distinct inputs from outputs. (SOPC 1, QSYS 0)

    Second, there is no distinction between lines and buses (?!?!?). When I use select tool which can be used to draw buses/lines once you're over the connection point, in Qsys it only draws lines, no buses. (SOPC 2, QSYS 0)

    Third, the complete symbol for Nios is a disaster - signals on one side only, all the lines/text inside the Nios symbol are overlapping, some text going out of the Nios symbol completely (usually signal names, but also some module names). The signal is completely different than all the other HDL symbols in our design. Good Altera, you've really made the distinction - all the other HDL symbols look great, while Nios looks terrible. Now it's really different, congrats. (SOPC 3, QSYS 0)

    Fourth, everytime I regenerate, the ports are randomized, as all of you guys noticed. (SOPC 4, QSYS 0)

    Fifth, anyone tried to edit the Nios symbol, so that it would look like something usable? It's impossible! Symbol editor has gone back ages from the previous versions of Quartus. (SOPC 5, QSYS 0)

    Sixth, address decoding for custom components is a mess. It was a bit hard in SOPC, well, now it doesn't work at all, thanks to the new merlin address router. (SOPC 6, QSYS 0)

    Productivity? Please, this is a joke.

    How can someone advertise a bad, buggy, unfinished product? And say it's better than SOPC? Increased productivity? :D They act like they never had a good product!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Unfortunately I run into those same issues as well... I was hoping very different kind of replies from this forum but seems like what I feared is quite true - for now at least.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ok, I updated the wiki page with issues that I've encountered. As for me, I'll stick with the SOPC until Qsys becomes usable.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    A quick note that might help a little re: changing port order with symbol generation... If you change the top-level signals of your Qsys system, you will have to regenerate a BSF symbol and will see the problem with the port-reordering. However, if you do not change the top-level signals of the Qsys system, and the system name is the same, you can turn off symbol generation (disable the .bsf checkbox on the Generation tab in Qsys), and just reuse the previously-generated symbol in your BDF so you don't have to change any of the port connections.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This is a very disappointing thread. I had hoped to find solutions, but apparently there are none!

    I just started playing with the new Qsys tool, and was at first impressed with how easily it converted my SOPC design. The GUI was even very similar to SOPC Builder, so it took no time at all to be ready to generate a new processor system. But then I opened up my Quartus schematic again and was appalled! The block it generated is practically unusable. If it is as randomly generated as it appears to be from the comments in this thread, I have no intention of mangling my schematic to fit a processor block that may change significantly the next time I edit the peripherals anyway.

    Thankfully the SOPC Builder tool is still included with V11.0, so I intend to continue using that. It looks like Altera still has their work cut out for them to make Qsys as user-friendly as SOPC Builder before expecting anyone to switch tools (other than those that switch by necessity due to the few technical enhancements...but as far as I can tell that really only applies to the minority right now).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes it is quite annoying having both pins on the same direction and even if there is no change and if we upate then also it gets change.

    So it is better that first time u just creat "HDL' file from your very first .bdf file then it will b pretty easy to change accordingly,not too much skill required,just check ur component interface singals with proper name and inseration is there or not.

    Try to make "HDL" that u created as a top level entity instead of that annoying bdf file otherwise most of ur time will get wasted on doing that useless stuff

    Hope this will help you.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I would skip having Qsys outputting symbols for now and using Quartus to convert the HDL top level into a symbol. Just make sure to regenerate the symbol any time you make a change that affects the top level of your system. The Qsys symbol generator is getting an overhaul so in later releases it should be a lot better.