QSys - Exporting an AXI4-Lite interface

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It's reasonably trivial to export an AXI3 or AXI4 interface from QSys to external HDL by instantiating an AXI Bridge. However AXI4-Lite is not available as a protocol option on this component.

It is available (and exportable) on an AXI Slave Agent (or AXI Master Agent) component but I see no way to use these components without building your own Qsys memory mapped interconnect since they expose the Qsys packet interface as Avalon-ST.

Is there an obvious way I'm missing to expose an AXI4 Lite interface such that I can connect an AXi4-Lite slave in external HDL?

(Quartus 15.1/Arria10)

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Which components are you talking about exactly? If you make a custom component, you can export any bridge that you want. Otherwise you could just export AXI4 and tie the lines to defaults, setting burst to 0.

The exact components I named in my initial question: "AXI Bridge" which has AXI3 and AXI4 as protocol option parameters, and "AXI Master Agent" & "AXI Slave Agent" which have AXI3/AXI4/AXI4Lite as protocol options in their parameters.

"AXI Bridge" is identified by Qsys documentation as the preferred route to export an AXI interface, and indeed its a fairly painless operation to add this component to a Qsys (sub)system and have Qsys integrate it into an automatically generated memory-mapped interconnect that uses the various QSys interconnect blocks (including "AXI Master Agent" & "AXI Slave Agent") under the hood. That does not give me a path to export an AXI4Lite mastering interface such that I can gluelessly connect an external AXI4Lite slave interface (typical of any modern CSR interface).

I could indeed write my own external AXI4->AXI4Lite bridge that decomposes any legal AXI4 burst and reflects ID's...but then again I could also write my own entire AXI interconnect and kick Qsys into touch, or any one of another half dozen workarounds to fix various ares of brokeness. At the end of the day it should do what it advertises, which is to auto generate arbitrary memory-mapped bus topologies that support (interchangeably via QSys interconnect): Avalon-MM, AXI3, AXI4, and AXI4Lite.

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The exact components I named in my initial question: "AXI Bridge" which has AXI3 and AXI4 as protocol option parameters, and "AXI Master Agent" & "AXI Slave Agent" which have AXI3/AXI4/AXI4Lite as protocol options in their parameters.

"AXI Bridge" is identified by Qsys documentation as the preferred route to export an AXI interface, and indeed its a fairly painless operation to add this component to a Qsys (sub)system and have Qsys integrate it into an automatically generated memory-mapped interconnect that uses the various QSys interconnect blocks (including "AXI Master Agent" & "AXI Slave Agent") under the hood. That does not give me a path to export an AXI4Lite mastering interface such that I can gluelessly connect an external AXI4Lite slave interface (typical of any modern CSR interface).

I could indeed write my own external AXI4->AXI4Lite bridge that decomposes any legal AXI4 burst and reflects ID's...but then again I could also write my own entire AXI interconnect and kick Qsys into touch, or any one of another half dozen workarounds to fix various ares of brokeness. At the end of the day it should do what it advertises, which is to auto generate arbitrary memory-mapped bus topologies that support (interchangeably via QSys interconnect): Avalon-MM, AXI3, AXI4, and AXI4Lite.

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You won't hear any disagreement with me on this one-- I've been fighting similar issues and have brought them up with Altera support. I'd put in a support ticket to at least let them know there is interest.

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So the crux of the matter is if "AXI Bridge" supported AXI4Lite as a protocol option in its parameters, then yes, you could drag-n-drop and export an AXI4Lite interface. However so far the only option I have found to expose an exportable AXI4Lite interface is to drop an "AXI Slave agent" (Confusing name...it acts as an AXI master) into the system. The problem with this is that this is a Qsys interconnect building block...it exposes a set of Avalon-ST interfaces that are transferring the internal Qsys interconnect protocol, and so far I've not seen a way to get Qsys to hook up these ports automatically to become part of a completed memory-mapped interconnect (AXI<->AXI)

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I believe that you need a translator in there as well; I haven't seen a way to get direct access to the interconnect myself, but if you find one, I'd be interested. I'm thinking that using AXI the best option might be to license an AMBA interconnect and configure it while exporting the HPS AXI interface directly.