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Altera_Forum's avatar
Altera_Forum
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12 years ago

pwm verilog code

Hi,

please help me to fnd pwm Verilog code

thank yu

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi,

    Your code will generate a wave that looks like a PWM !

    To create a PWM you need a duty cycle (how often do you want to refresh your signal) : You need to know your board frequency and compute the duty of your PWM ...

    The link I gave you explain that ! Follow the steps and stop jumping into coding something you don't understand

    I recommend you read the page carefully
  • Altera_Forum's avatar
    Altera_Forum
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    Hi,

    I hope this idea is correct.

    my fpga clock is 50mhz.that is period 20ns.

    I designed a pwm with 1000ns period.

    switch variable given as 2 to get 80 percent duty cycle.

    please check.

    Thankyou
  • Altera_Forum's avatar
    Altera_Forum
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    1000 ns =>

    P = 0.000001*50000000 = 50

    SC (Steps Count) = 2^3 = 8

    ==> sd = P / SC = 50/8 =6.25

    but you are using sd = 20 !

    Please read carefully the page (link I posted) and follow the steps ! It's not that hard !
  • Altera_Forum's avatar
    Altera_Forum
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    Hi,

    what is mean by refreshing signal?? I didn't get. can't i take p=1000ns?
  • Altera_Forum's avatar
    Altera_Forum
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    by refreshing signal we mean the time we need to have a new value (period)

    Yes you can take whatever period you want ! For 1000 ns P = 50 (because you multiply the 20 ns by 50 to get 1000 ns)