Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Push data pairs into stack

Hello everyone,

I'm doing image processing on FPGA, i'am programming connected component labeling exactly.

So the problem is, that i have reached to program a stack for a certain purpose but i need to have an entry pair data (L min,L max) not just an input vector.

I though about records but i don't think it is the right solution.

I would be very grateful if you could help me clarify this matter.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    This is a very vague question - are you sure you meant to post this in the VHDL section?

    What is exactly the problem? do you have some code showing the problem and better explain what you're trying to do?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I will make it so simple. I just want to to know how to write this in vhdl :

    stack(ptr)<= (data_in1,data_in2) instead of stack(ptr)<=data_in.

    I can post the hole code and explain you the code and the project but i 'am afraid that i will complicate the idea because all i need is just what i wrote above.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    just make the stack twice as wide and concatenate data_in1 and data_in2:

    stack(ptr) <= data_in1 & data_in2;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    This is my code for stack : 

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stack is
generic( WIDTH : positive := 8 ; DEPTH : positive := 4);
port( Clk : in std_logic; .
Data_In : in std_logic_vector(WIDTH-1 downto 0);
Data_Out : out std_logic_vector(WIDTH-1 downto 0); 
PUSH_barPOP,in_fv,in_dv : in std_logic; 
stack_Full : out std_logic; 
stack_Empty : out std_logic 
);
end stack;
architecture Behavioral of stack is
type mem_type is array (DEPTH-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal stack_mem : mem_type := (others => (others => '0'));
signal stack_ptr : integer := DEPTH-1;
signal full,empty : std_logic := '0';
begin
stack_Full <= full; 
stack_Empty <= empty;
PUSH : process(Clk)
begin
if(rising_edge(Clk)) then
if in_fv='1' then 
if in_dv='1' then
if ( PUSH_barPOP = '1' and full = '0') then
stack_mem(stack_ptr) <= Data_In;
if(stack_ptr /= 0) then
stack_ptr <= stack_ptr - 1;
end if; 
--setting full and empty flags
if(stack_ptr = 0) then
full <= '1';
empty <= '0';
elsif(stack_ptr = DEPTH-1) then
full <= '0';
empty <= '1';
else
full <= '0';
empty <= '0';
end if;
end if;
else 
if (PUSH_barPOP = '0' and empty = '0') then
Data_Out <= stack_mem(stack_ptr);
if(stack_ptr /= DEPTH-1) then 
stack_ptr <= stack_ptr + 1; 
end if; 
if(stack_ptr = 0) then
full <= '1';
empty <= '0';
elsif(stack_ptr = DEPTH-1) then
full <= '0';
empty <= '1';
else
full <= '0';
empty <= '0';
end if; 
end if;
end if;
end if;
end if; 
end process;
end Behavioral;

    So for this line : stack_mem(stack_ptr) <= Data_In; my Data_In is actually a data pair and i need it to be like this

    stack_mem(stack_ptr) <= (Data_In1,Data_In1).

    I don't know how is it possible with vhdl .

    Any idea please ?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    What you are doing here is no different from concatenating the two inputs. You're storing 2 words at the same memory location.

    As for your error - I dont know what it's refering to. Have you tried running this code in modelsim yourself, rather than via the quartus gui?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    I will try your solution. Thank you so much for your help.