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Altera_Forum's avatar
Altera_Forum
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18 years ago

Pulse Generation - Need Help

Hello all,

Following is a code that transfers paralle data to the output serially. I also need to generate two ouptut pulses (e.g. WRb and IOUD) that would low and high after the output transfer and then back to their originial state. 


process (syncon, Reset) 
begin  
	if (Reset='1') then
		counter<=0; 
		Address<=b"000000";
		Data <=b"00000000";
		WRb<='1';
		IOUD<='0';
	elsif (syncon'Event and syncon='1') then 
						
			if(counter=0 and start1=1) then 
				Address  <= b"000100"; 
				Data <=  reg0;
				counter<=1; 
				WRb <= '0' ; 	
				IOUD <= '1'; 
				
			elsif(counter=1 and start1=1) then
				Address  <= b"000101"; 
				Data <= reg1;
				WRb <= '0'; 	
				IOUD <= '1';
							
			end if; 
	elsif (syncon'Event and syncon='0') then 			
			WRb <= '1'; 	
			IOUD <= '0';
	end if; 
end process; 
end programmer;

I have tried to use the following two statemetns

elsif (syncon'Event and syncon='1') then

elsif (syncon'Event and syncon='0') then

and then gave opposite state values so that it will form a pulse. I get the error "Error (10822): HDL error at programmer.vhd(66): couldn't implement registers for assignments on this clock edge" on the above two lines.

What seems to be the problem and how can I resolve it ?

Many Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    When you want to generate WRb and IOUD from synchronous logic (strongly advisable to avoid glitches with the signals), they can't change there state on both clock edges. As you already assigned the signals on rising edge for two condidtions in a process, they only could be assigned in the same process, also on rising clock edge. You didn't tell the intended conditions, but it's surely possible to extent the state machine alike deocding construct to reflect the intended conditions.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi all,

    I was looking about to see if I could find something in an older post, and this was the closest but still hasn't helped me from what I could see.

    I currently have the error:

    "error (10822): hdl error at lvds_fifo_control.vhd(210): couldn't implement registers for assignments on this clock edge"

    But I'm not trying to assign things on the rising and falling edge of a clock in the same process as was explained here.

    Instead I have 2 clocks, one is 3x the frequency of the other (done using a PLL), and I am basically trying to multplex 24 bit parrallel input and load it into an 8bit wide FIFO. I know my error has something to do with the fact that I am trying to load the first of the 3 bytes into the FIFO when both clocks have their rising edge, Load_FIFO is high, and the FIFO buffer is not full.... but I am not sure what is causing my error....

    I have probably done something extremely obvious wrong but can't seem to work it out, as I have little experience with VHDL...

    If not, is there a better way to implement what I am trying to do? 

     
--------------------------------------------------------------------------------
-- FIFO Loader
--------------------------------------------------------------------------------
 FIFO_Loader : process (intRCLK, MULT_CLK, rst, Load_FIFO, FIFO_FULL)
 
 begin
 
 if (rst = '1') then
  FIFO_WR <= '0';
  Load_State <= Load_IDLE;
 elsif ((MULT_CLK'EVENT) and (MULT_CLK='1')) then
  case Load_State is
 
  --Idle state....
   when Load_IDLE =>
    if ((intRCLK'EVENT) and (intRCLK = '1') and (Load_FIFO = '1') and (FIFO_FULL = '0')) then --
     FIFO_WR <= '1';
     FIFO_IN(0) <= R(0);
     FIFO_IN(1) <= R(1);
     FIFO_IN(2) <= R(2);
     FIFO_IN(3) <= R(3);
     FIFO_IN(4) <= R(4);
     FIFO_IN(5) <= R(5);
     FIFO_IN(6) <= G(0);
     FIFO_IN(7) <= G(1);
     Load_State <= Load_Byte2;
    else
     FIFO_WR <= '0';
     Load_State <= Load_IDLE;
    end if;
 
   when Load_Byte2 =>
     FIFO_WR <= '1';
     FIFO_IN(0) <= G(2);
     FIFO_IN(1) <= G(3);
     FIFO_IN(2) <= G(4);
     FIFO_IN(3) <= G(5);
     FIFO_IN(4) <= B(0);
     FIFO_IN(5) <= B(1);
     FIFO_IN(6) <= B(2);
     FIFO_IN(7) <= B(3);
     Load_State <= Load_Byte3;
 
   when Load_Byte3 =>
     FIFO_WR <= '1';
     FIFO_IN(0) <= B(4);
     FIFO_IN(1) <= B(5);
     FIFO_IN(2) <= H_Sync;
     FIFO_IN(3) <= V_Sync;
     FIFO_IN(4) <= Reserved(0);
     FIFO_IN(5) <= Reserved(1);
     FIFO_IN(6) <= Reserved(2);
     FIFO_IN(7) <= Reserved(3);
     Load_State <= Load_IDLE;
 
  -- default state - return to IDLE
  when others =>
     FIFO_WR <= '0';
     Load_State <= Load_IDLE;
 
  end case;
 end if;
   end process FIFO_Loader;

    Cheers,

    Lee H
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I kept looking through the forums and found this thread....

    http://alterauserforum.net/forum/showthread.php?p=6441

    Looks like I cant have my if statment involving the second clock within my case statement....

    I'm going to see how I can rearrange this, but if there are any better ways of doing this then please feel free to let me know!

    Cheers,

    Lee