Pulse Generation - Need Help

When you want to generate WRb and IOUD from synchronous logic (strongly advisable to avoid glitches with the signals), they can't change there state on both clock edges. As you already assigned the signals on rising edge for two condidtions in a process, they only could be assigned in the same process, also on rising clock edge. You didn't tell the intended conditions, but it's surely possible to extent the state machine alike deocding construct to reflect the intended conditions.