Pulse Generation - Need Help

Hi all,

I was looking about to see if I could find something in an older post, and this was the closest but still hasn't helped me from what I could see.

I currently have the error:

"error (10822): hdl error at lvds_fifo_control.vhd(210): couldn't implement registers for assignments on this clock edge"

But I'm not trying to assign things on the rising and falling edge of a clock in the same process as was explained here.

Instead I have 2 clocks, one is 3x the frequency of the other (done using a PLL), and I am basically trying to multplex 24 bit parrallel input and load it into an 8bit wide FIFO. I know my error has something to do with the fact that I am trying to load the first of the 3 bytes into the FIFO when both clocks have their rising edge, Load_FIFO is high, and the FIFO buffer is not full.... but I am not sure what is causing my error....

I have probably done something extremely obvious wrong but can't seem to work it out, as I have little experience with VHDL...

If not, is there a better way to implement what I am trying to do?

 
--------------------------------------------------------------------------------
-- FIFO Loader
--------------------------------------------------------------------------------
 FIFO_Loader : process (intRCLK, MULT_CLK, rst, Load_FIFO, FIFO_FULL)
 
 begin
 
 if (rst = '1') then
  FIFO_WR <= '0';
  Load_State <= Load_IDLE;
 elsif ((MULT_CLK'EVENT) and (MULT_CLK='1')) then
  case Load_State is
 
  --Idle state....
   when Load_IDLE =>
    if ((intRCLK'EVENT) and (intRCLK = '1') and (Load_FIFO = '1') and (FIFO_FULL = '0')) then --
     FIFO_WR <= '1';
     FIFO_IN(0) <= R(0);
     FIFO_IN(1) <= R(1);
     FIFO_IN(2) <= R(2);
     FIFO_IN(3) <= R(3);
     FIFO_IN(4) <= R(4);
     FIFO_IN(5) <= R(5);
     FIFO_IN(6) <= G(0);
     FIFO_IN(7) <= G(1);
     Load_State <= Load_Byte2;
    else
     FIFO_WR <= '0';
     Load_State <= Load_IDLE;
    end if;
 
   when Load_Byte2 =>
     FIFO_WR <= '1';
     FIFO_IN(0) <= G(2);
     FIFO_IN(1) <= G(3);
     FIFO_IN(2) <= G(4);
     FIFO_IN(3) <= G(5);
     FIFO_IN(4) <= B(0);
     FIFO_IN(5) <= B(1);
     FIFO_IN(6) <= B(2);
     FIFO_IN(7) <= B(3);
     Load_State <= Load_Byte3;
 
   when Load_Byte3 =>
     FIFO_WR <= '1';
     FIFO_IN(0) <= B(4);
     FIFO_IN(1) <= B(5);
     FIFO_IN(2) <= H_Sync;
     FIFO_IN(3) <= V_Sync;
     FIFO_IN(4) <= Reserved(0);
     FIFO_IN(5) <= Reserved(1);
     FIFO_IN(6) <= Reserved(2);
     FIFO_IN(7) <= Reserved(3);
     Load_State <= Load_IDLE;
 
  -- default state - return to IDLE
  when others =>
     FIFO_WR <= '0';
     Load_State <= Load_IDLE;
 
  end case;
 end if;
   end process FIFO_Loader;  

Cheers,

Lee H