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mschiller-nrao's avatar
mschiller-nrao
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10 months ago

Proper way to infer Quad Port Ram?

I generated the Quad Port Template in Quartus 2025.3.  I then wrapped it into a wrapper and finally into my design. This is then instantiated with the following generics: Info(19337): VHDL info a...
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mschiller-nrao's avatar
mschiller-nrao
Icon for New Contributor rankNew Contributor
10 months ago

As another point of information.  I tried synthesizing the inferred quad_port_ram outside my design.   For reasonable size blocks eg 2048 deep x 32 wide the file inferred properly.  But I appear to start having problems as the block gets wider.  So I'm assuming this is some kind of synthesis bug where the wide ram (like 500x2048!) triggers the bug.  But it does work with the altera_syncram (basically the IP) solution....

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    9 months ago

    What is the problem you are facing? Which parameter setting caused the issue? Please provide more details.
    Additionally, what specific memory configuration setting do you plan to use?