New Contributor
New ContributorSorry I didn't make that clear This is an AgileX I-series part.
For now I've gotten it to work with effectively an IP core.. I generated the IP core, and then reverse engineered what it was calling to use the primitive/megafunction directly. (eg altera_syncram). But I hate that solution because for quad port it seems that only the altera_mf_ver (verilog) library even has the altera_syncram model [and for some reason the sim library calls it altera_syncram_derived instead of altera_syncram?!?!]
I'm a VHDL shop, so any verilog in my code base pisses me off because I can't use opensource simulators. [I do have a single seat of rivierapro... which I'm using to simulate this solution]
