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Altera_Forum
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11 years ago

Propagation Delay for SPI bus routed through MAX II CPLD

Hello All, I have a question regarding routing an SPI bus through a MAX II CPLD. I am using the set_max_delay to constrain the pin to pin delay on the SPI lines (MISO,MOSI,CLK,CSN), but I have ...
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Altera_Forum
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11 years ago

If you use registers in your vhdl/verilog then you might try the fast input/output register option in the assignment editor for the relevant IO pins to improve timing.