Project 1- Fully associative cache

--- Quote Start ---

Hey guys, i'm studying computer engineering and I got a project to do in Quartus II. The project is about a Fully Associative Cache designed in quartus II (schematic Design ) with 3 specifications: 1- 64Locaation 2- 32bit data 3- 8 bit tag. can anyone help me please? i'll be thankful :)

--- Quote End ---

Did you already think about the project?

What is a "Fully Associative Cache"?

What should the Fpga do?

Ok, now I know a little more about the Fully associative cache.

http://www.nt.fh-koeln.de/vogt/bs/animationen/cacheanimation.pdf

Sorry, it is in german.

Well, I think you need to generate a Single Ported Ram (SPR) with the Altera Megawizard.

Next you can write a Vhdl module that can search and has read/write connection to your SPR.

--- Quote Start ---

I just need to do the schematic design

--- Quote End ---

But you are allowed to use Vhdl, aren't you?

I have no idea, how you can do this with a few gates or some "black boxes" in the schematic.

You can implement it in vhdl and "import" the module into the schematic.

--- Quote Start ---

Can I contact you on Skype or MSN if it's okay ?

--- Quote End ---

I'm sorry but I have no cam and no mic here.

Just send me a private mail and I'll answer.

You won't find someone to do your homework for you here, but if you start doing something on your own and face any problems, you can ask any specific question here.

I find it strange that you have to do something like that with schematics. It would be a lot easier with HDL in my opinion.