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Altera_Forum's avatar
Altera_Forum
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12 years ago

Project 1- Fully associative cache

Hey guys, i'm studying computer engineering and I got a project to do in Quartus II. The project is about a Fully Associative Cache designed in quartus II (schematic Design ) with 3 specifications: 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I just need to do the schematic design

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But you are allowed to use Vhdl, aren't you?

I have no idea, how you can do this with a few gates or some "black boxes" in the schematic.

You can implement it in vhdl and "import" the module into the schematic.