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Altera_Forum's avatar
Altera_Forum
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12 years ago

Project 1- Fully associative cache

Hey guys, i'm studying computer engineering and I got a project to do in Quartus II. The project is about a Fully Associative Cache designed in quartus II (schematic Design ) with 3 specifications: 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Ok, now I know a little more about the Fully associative cache.

http://www.nt.fh-koeln.de/vogt/bs/animationen/cacheanimation.pdf

Sorry, it is in german.

Well, I think you need to generate a Single Ported Ram (SPR) with the Altera Megawizard.

Next you can write a Vhdl module that can search and has read/write connection to your SPR.