Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, VHDL and FPGAs but feel I am making some progress slowly. I have some bidirectional signals in my design, and in my testbench want to be able to put some inputs/stimuli into these, but also be able to see the outputs in the generated "wave" signal plot, as at the moment the values seem fine when acting as inputs but just give an X when they should be outputs as they are being assigned by both the test bench and my design but in different directions. Any help is much appreciated even if its just a link to a clear explanation or example... I'm trying to look into it now, but so far haven't found anything that clear or a nice example... Cheers

Usually designers use bidirectional signals on pins and not internally. input state: Your testbench should drive these pins when they are inputs to your DUT. Here your DUT can read them but should apply tristate(Z) i.e.cutoff logic. output state: Your DUT should drive them when they are outputs. testbench can read them. The io blocks have tristate buffer that is switched off if Z applied. Internally no such buffer exists but can be emulated in logic but as mentioned, there is no need to use them internally.

Hi, Are you sure about your "bidirectional" design ? Have you wrote the 'z' for the case where your bidir is in inuput mode ? 'x' means forcing unkown : it is 0 or 1 but it often means that there is conflict. Your bidir is in ouput mode and your stimuli force this signal at the same time. (not verified myself, i may be wrong) in quartus, you have templates available in menu when you edit vhdl. In literature section on altera website, you will find example. You have to check both your design and your testbench. Keep in mind that VHDL is just a description langage (not a program). Could you post your design and testbench ?

you need to drive "ZZZZZZZZ" onto AD and AC when you expect signals to come out of the DUT. Bidirectional signals are otherwise best avoided.

--- Quote Start --- you need to drive "ZZZZZZZZ" onto AD and AC when you expect signals to come out of the DUT. Bidirectional signals are otherwise best avoided. --- Quote End --- Ah I knew I had to do something like this but was just trying to drive AD to 'Z' rather than "ZZZZZZZZ"... Cheers, I'll give this a try...

Problems with bidirectional signals in VHDL Testbench for ModelSim

18 Replies

Altera_Forum
Honored Contributor
12 years ago
Why not post the code and the errors.
Altera_Forum
Honored Contributor
12 years ago
this is the overview of my program.....the problem is in port maping .if i maped port in clockwise direction then what can i do for counter clock wise portmaping.?
Altera_Forum
Honored Contributor
12 years ago
THis would be a single entity, you wouldnt need any port mapping.
Post the code and the errors and we can help.
Altera_Forum
Honored Contributor
12 years ago
if (sel= 0) then
ch0: noc
PORT MAP(
clk => clk,
reset => reset,
data_in => mDch_buffer0,
parity_in =>mPch_buffer0,
bflag_in => mch0_busy,
--bflag_out : out std_logic;
parity_out => mP_buffer1, ---line 950
data_out =>mD_buffer1 );
elsif (sel= 1) then---- line 952
PORT MAP(
clk => clk,
reset => reset,
data_in => mDch_buffer1,
parity_in =>mPch_buffer1,
bflag_in => mch0_busy,
--bflag_out : out std_logic;
parity_out => mP_buffer0,
data_out =>mD_buffer0 );
end if;
** Error: C:/Modeltech_5.7g/examples/nov5.vhd(950): near ";": expecting: ')'
** Error: C:/Modeltech_5.7g/examples/nov5.vhd(952): near "then": expecting: <= :=
Altera_Forum
Honored Contributor
12 years ago
you cannot put an instantiation inside a process.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
if (sel= 0) then
ch0: noc
PORT MAP(
clk => clk,
reset => reset,
data_in => mDch_buffer0,
parity_in =>mPch_buffer0,
bflag_in => mch0_busy,
--bflag_out : out std_logic;
parity_out => mP_buffer1, ---line 950
data_out =>mD_buffer1 );
elsif (sel= 1) then---- line 952
PORT MAP(
clk => clk,
reset => reset,
data_in => mDch_buffer1,
parity_in =>mPch_buffer1,
bflag_in => mch0_busy,
--bflag_out : out std_logic;
parity_out => mP_buffer0,
data_out =>mD_buffer0 );
end if;
** Error: C:/Modeltech_5.7g/examples/nov5.vhd(950): near ";": expecting: ')'
** Error: C:/Modeltech_5.7g/examples/nov5.vhd(952): near "then": expecting: <= :=
--- Quote End ---

what you need in this case is one port map but then connect signals in the logic. e.g

port map ... data_in => data_in, data_out => data_out, ... then in your logic: if sel = '0' then data_in <= mDch_buffer0; mD_buffer1 <= data_out; else data_in <= mDch_buffer1; mD_buffer0 <= data_out; end if;
Altera_Forum
Honored Contributor
12 years ago
i started t resolve my solution from base .
this is the simple counter program of my project .

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port( clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
busy : out std_logic;
dcount: out std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;

architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
signal dec: std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if reset = '1' then
pre_count <= "0000";
busy<='0';
elsif (clk='1' and clk'event) then
if load = '1' then
dec<=data;
busy<='1';

elsif dec >0 then
dec<=dec-'1';
pre_count <= pre_count + "1";
elsif dec= 0 then
busy<='0';

end if;
end if;
end process;
dcount <=dec;
count <= pre_count;
end behav;

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity counter_tb is
end;

architecture counter_tb of counter_tb is

COMPONENT counter
PORT ( clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
busy : out std_logic;
dcount: out std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0) );
END COMPONENT ;

SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL load,cheko : std_logic := '0';
Signal data: std_logic_vector(3 downto 0):="1010" ;
SIGNAL busy : std_logic;
SIGNAL count : std_logic_vector(3 downto 0);
signal dcount: std_logic_vector(3 downto 0);

begin

dut : counter
PORT MAP (
count => count,
clk => clk,
load=> load,
busy=> busy,
data=> data,
dcount =>dcount,
reset => reset );

chekoo : PROCESS
begin
if ( busy ='1') then
cheko <='1';
elsif ( busy ='0') then
cheko <='0';
else
cheko <='0';
end if;
end process chekoo;

clock : PROCESS
begin
wait for 1 ns; clk <= not clk;
end PROCESS clock;

stimulus : PROCESS
begin
load <= '0';
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait for 4 ns; load <= '1';
wait for 2 ns; load <= '0';
wait;
end PROCESS stimulus;

end counter_tb;

WARNING[2]: C:/Modeltech_5.7g/examples/nov5.vhd(93): Possible infinite loop: process has no wait statement.
Altera_Forum
Honored Contributor
12 years ago
All processes must have either a wait statement or a sensitivity list, otherwise they will loop forever in 0 time. You chekkoo process probably needs a sensitivity list with bust in it.

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Problems with bidirectional signals in VHDL Testbench for ModelSim

18 Replies

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