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Altera_Forum
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15 years ago

Problems with bidirectional signals in VHDL Testbench for ModelSim

Hi all, I was just wondering if there is a simple way of implimenting bidirectional signals in a VHDL testbench I'm using ModelSim - Altera Starter Edition 6.5e and am very new to Quartus II, ...
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Altera_Forum
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12 years ago

All processes must have either a wait statement or a sensitivity list, otherwise they will loop forever in 0 time. You chekkoo process probably needs a sensitivity list with bust in it.