Problems with bidirectional signals in VHDL Testbench for ModelSim

i started t resolve my solution from base .

this is the simple counter program of my project .

library ieee ;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

port( clk: in std_logic;

reset: in std_logic;

load: in std_logic;

data: in std_logic_vector(3 downto 0);

busy : out std_logic;

dcount: out std_logic_vector(3 downto 0);

count: out std_logic_vector(3 downto 0)

);

end counter;

architecture behav of counter is

signal pre_count: std_logic_vector(3 downto 0);

signal dec: std_logic_vector(3 downto 0);

begin

process(clk,reset)

begin

if reset = '1' then

pre_count <= "0000";

busy<='0';

elsif (clk='1' and clk'event) then

if load = '1' then

dec<=data;

busy<='1';

elsif dec >0 then

dec<=dec-'1';

pre_count <= pre_count + "1";

elsif dec= 0 then

busy<='0';

end if;

end if;

end process;

dcount <=dec;

count <= pre_count;

end behav;

library ieee ;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_textio.all;

use std.textio.all;

entity counter_tb is

end;

architecture counter_tb of counter_tb is

COMPONENT counter

PORT ( clk: in std_logic;

reset: in std_logic;

load: in std_logic;

data: in std_logic_vector(3 downto 0);

busy : out std_logic;

dcount: out std_logic_vector(3 downto 0);

count: out std_logic_vector(3 downto 0) );

END COMPONENT ;

SIGNAL clk : std_logic := '0';

SIGNAL reset : std_logic := '0';

SIGNAL load,cheko : std_logic := '0';

Signal data: std_logic_vector(3 downto 0):="1010" ;

SIGNAL busy : std_logic;

SIGNAL count : std_logic_vector(3 downto 0);

signal dcount: std_logic_vector(3 downto 0);

begin

dut : counter

PORT MAP (

count => count,

clk => clk,

load=> load,

busy=> busy,

data=> data,

dcount =>dcount,

reset => reset );

chekoo : PROCESS

begin

if ( busy ='1') then

cheko <='1';

elsif ( busy ='0') then

cheko <='0';

else

cheko <='0';

end if;

end process chekoo;

clock : PROCESS

begin

wait for 1 ns; clk <= not clk;

end PROCESS clock;

stimulus : PROCESS

begin

load <= '0';

wait for 5 ns; reset <= '1';

wait for 4 ns; reset <= '0';

wait for 4 ns; load <= '1';

wait for 2 ns; load <= '0';

wait;

end PROCESS stimulus;

end counter_tb;

WARNING[2]: C:/Modeltech_5.7g/examples/nov5.vhd(93): Possible infinite loop: process has no wait statement.