Problems with bidirectional signals in VHDL Testbench for ModelSim

--- Quote Start ---

if (sel= 0) then

ch0: noc

PORT MAP(

clk => clk,

reset => reset,

data_in => mDch_buffer0,

parity_in =>mPch_buffer0,

bflag_in => mch0_busy,

--bflag_out : out std_logic;

parity_out => mP_buffer1, ---line 950

data_out =>mD_buffer1 );

elsif (sel= 1) then---- line 952

PORT MAP(

clk => clk,

reset => reset,

data_in => mDch_buffer1,

parity_in =>mPch_buffer1,

bflag_in => mch0_busy,

--bflag_out : out std_logic;

parity_out => mP_buffer0,

data_out =>mD_buffer0 );

end if;

** Error: C:/Modeltech_5.7g/examples/nov5.vhd(950): near ";": expecting: ')'

** Error: C:/Modeltech_5.7g/examples/nov5.vhd(952): near "then": expecting: <= :=

--- Quote End ---

what you need in this case is one port map but then connect signals in the logic. e.g

port map
...
data_in => data_in,
data_out => data_out,
...
then in your logic:
if sel = '0' then
    data_in <= mDch_buffer0;
    mD_buffer1 <= data_out;
else
    data_in <= mDch_buffer1;
    mD_buffer0 <= data_out;
end if;