Forum Discussion
ELupo
New Contributor
New ContributorProblems simulating ADC in DE10-Lite board using Quartus Prime Lite Edition 19.1 in VHDL designs, and at gate level in verilog designs
Our course at ETSEIB-UPC is actually based in DE0 Cyclone III board and VHDL using an old version of Quartus II. We are analyzing to move to DE10-Lite board and VHDL using Quartus Prime Lite Edition...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi ,
I would recommend to use the ADC IP , there was an issue with VHDL simulation previously. With my understanding the issue got resolved in new version of quartus.
I would recommend to use new Standard version of Quartus .
