Problems instantiating qsys component within VHDL help

Hi,

I have generated a Nios II system with qsys and am trying to write a top-level VHDL which wraps it as shown below but I am getting the following errors. CLOCK_50 , KEY and SW are the exact sames in the nios_qsys.v generated from qsys so I don't know what the issue is. Does anyone know how to solve it? Thanks

Error (10349): VHDL Association List error at lights.vhd(35): formal "clk_clk" does not exist

Error (10346): VHDL error at lights.vhd(33): formal port or parameter "CLOCK_50" must have actual or default value

Error (10784): HDL error at lights.vhd(25): see declaration for object "CLOCK_50"

Error (10346): VHDL error at lights.vhd(33): formal port or parameter "KEY" must have actual or default value

Error (10784): HDL error at lights.vhd(26): see declaration for object "KEY"

Error (10346): VHDL error at lights.vhd(33): formal port or parameter "SW" must have actual or default value

Error (10784): HDL error at lights.vhd(27): see declaration for object "SW"

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
----------------------------------------------------------------------------------------------------------------
ENTITY lights IS
PORT (
	CLOCK_50 : IN STD_LOGIC;
	KEY : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
	SW : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	LEDG : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lights;
------------------------------------------------------------------------------------
ARCHITECTURE lights_rtl OF lights IS
	COMPONENT nios_qsys
	PORT (
		SIGNAL CLOCK_50: IN STD_LOGIC;
		SIGNAL KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
		SIGNAL SW : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		SIGNAL LEDG : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;
BEGIN
NiosII : nios_qsys
	PORT MAP(
		clk_clk => CLOCK_50,
		reset_reset_n => KEY(0),
		switch_in_export => SW(7 DOWNTO 0),
		led_out_export => LEDG(7 DOWNTO 0)
	);
END lights_rtl;