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Altera_Forum
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11 years ago

Problems instantiating qsys component within VHDL help

Hi, I have generated a Nios II system with qsys and am trying to write a top-level VHDL which wraps it as shown below but I am getting the following errors. CLOCK_50 , KEY and SW are the exact ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If you are trying to simulate the Qsys design with your top level, you need to generate the simulation files and then change the tcl script to include your top level. It will compile all the files needed for the qsys system.