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Altera_Forum's avatar
Altera_Forum
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11 years ago

Problems instantiating qsys component within VHDL help

Hi, I have generated a Nios II system with qsys and am trying to write a top-level VHDL which wraps it as shown below but I am getting the following errors. CLOCK_50 , KEY and SW are the exact ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You've got the port mapping the wrong way round, it needs to be

port => local_signal

But the code you posted doesnt have signals called "clk_clk" , reset_reset_n, switch_in_export or led_out_export. Where do these come from?

Also, when mapping VHDL to a verilog component, you must get the case sensitivity correct.