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Altera_Forum's avatar
Altera_Forum
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15 years ago

Problem wuth altsyncram

Hi,

I included in a top level schematic design an altsyncram function.

I configured the altsyncram with MegaWizard as a true dual port ram (both rd and wr on each port), 8 bit wide and 4096 deep.

When I compile in Quartus I get these error messages: 

Error: WYSIWYG primitive "ram_block1a0" must use clk0 port
Error: WYSIWYG primitive "ram_block1a1" must use clk0 port
Error: WYSIWYG primitive "ram_block1a2" must use clk0 port
Error: WYSIWYG primitive "ram_block1a3" must use clk0 port
Error: WYSIWYG primitive "ram_block1a4" must use clk0 port
Error: WYSIWYG primitive "ram_block1a5" must use clk0 port
Error: WYSIWYG primitive "ram_block1a6" must use clk0 port
Error: WYSIWYG primitive "ram_block1a7" must use clk0 port

When I click on one of the error messages, Quartus open the attached auto generated file and points to one of the lines 

ram_block1a0 : cycloneiii_ram_block

I see in the \db subdirectory a lot of other auto generated files altsyncram_*.tdf ; is this correct?

Please help

Regards

Cris

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    This is what I understood.

    But the clock is actually already connected: single clock for both ram ports.

    Any other suggestion?

    I changed mem depth, added separated clocks for each port, regenerated the component, but always the same error.

    I generated HDL from bdf schematic and all seems to be ok.

    You can see the clock connection is there. clk_50m comes from a pll and feeds other devices, too.

    Verilog: 

    
dp_ram    b2v_inst24(
    .wren_a(ext_wren),
    .rden_a(ext_rden),
    .wren_b(dsp_wren),
    .rden_b(dsp_rden),
    .clock(clk_50m),
    .aclr(resetn),
    .address_a(ext_addr),
    .address_b(dsp_addr),
    .data_a(ext_data),
    .data_b(dsp_data),
    .q_a(ext_data),
    .q_b(dsp_data));

    VHDL: 

    
b2v_inst24 : dp_ram
PORT MAP(wren_a => ext_wren,
         rden_a => ext_rden,
         wren_b => dsp_wren,
         rden_b => dsp_rden,
         clock => clk_50m,
         aclr => resetn,
         address_a => ext_addr(12 DOWNTO 0),
         address_b => dsp_addr(12 DOWNTO 0),
         data_a => ext_data(7 DOWNTO 0),
         data_b => dsp_data,
         q_a => ext_data(7 DOWNTO 0),
         q_b => dsp_data);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I instantiated the same altsyncram component in a blank design and Quartus processes it perfectly without errors.

    Could it be a conflict with the sopc builder system I have in the original target design?

    Infact I see that sopc builder auto generates other altsyncram*.tdf file in the \db directory. I checked them and they all seem similar to the one generated for my altsyncram.

    I changed a few parameters in Wizard int order my altsyncram exactly matches one of those sopc files (apart the name...) but I always get the same error.

    Please, any help is greatly appreciated because I've been stuck on this point for two days so far.

    Cris
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    I instantiated the same altsyncram component in a blank design and Quartus processes it perfectly without errors.

    Could it be a conflict with the sopc builder system I have in the original target design?

    Infact I see that sopc builder auto generates other altsyncram*.tdf file in the \db directory. I checked them and they all seem similar to the one generated for my altsyncram.

    I changed a few parameters in Wizard int order my altsyncram exactly matches one of those sopc files (apart the name...) but I always get the same error.

    Please, any help is greatly appreciated because I've been stuck on this point for two days so far.

    Cris

    --- Quote End ---

    your clock has no connection!!!!!!!!!!!!!!!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi Cris,

    By definition, a Dual Port RAM has Port A and Port B. Thus it will also have two Clocks ( clockA and clockB ). It looks like you have not connected the clock for Port A in your design. Please check and connect the clock port for Port A to the same clk_50m signal. Make sure you're instance has the correct port definitions.

    Thanks

    Abr
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi chinaboy and eapenabrm,

    thank you for your kind answers but please note that the thread is 7 years old!!!

    The problem had surely been solved. I can't remember, but taking a rapid look at the code, I guess the problem was actually with the level of resetn signal, since the clock connection in my final (working) design is exactly as the one I had pasted above: the only difference is a negated ~resetn.

    I don't know the reason of that misleading Quartus error messages.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hey Cris,

    No issues, I was just checking to see if my ID still work in this forum. Its been like 10 years for me since I first logged into this, was just checking to see if things still work. Didn't want to use an active thread, so picked an old one to do it. Thanks anyways.:)

    Abr