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Altera_Forum
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16 years ago

Problem wuth altsyncram

Hi, I included in a top level schematic design an altsyncram function. I configured the altsyncram with MegaWizard as a true dual port ram (both rd and wr on each port), 8 bit wide and 4096 deep...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi Cris,

By definition, a Dual Port RAM has Port A and Port B. Thus it will also have two Clocks ( clockA and clockB ). It looks like you have not connected the clock for Port A in your design. Please check and connect the clock port for Port A to the same clk_50m signal. Make sure you're instance has the correct port definitions.

Thanks

Abr