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Altera_Forum
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16 years ago

Problem wuth altsyncram

Hi, I included in a top level schematic design an altsyncram function. I configured the altsyncram with MegaWizard as a true dual port ram (both rd and wr on each port), 8 bit wide and 4096 deep...
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Altera_Forum
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9 years ago

Hi chinaboy and eapenabrm,

thank you for your kind answers but please note that the thread is 7 years old!!!

The problem had surely been solved. I can't remember, but taking a rapid look at the code, I guess the problem was actually with the level of resetn signal, since the clock connection in my final (working) design is exactly as the one I had pasted above: the only difference is a negated ~resetn.

I don't know the reason of that misleading Quartus error messages.