Problem wuth altsyncram

This is what I understood.

But the clock is actually already connected: single clock for both ram ports.

Any other suggestion?

I changed mem depth, added separated clocks for each port, regenerated the component, but always the same error.

I generated HDL from bdf schematic and all seems to be ok.

You can see the clock connection is there. clk_50m comes from a pll and feeds other devices, too.

Verilog:

dp_ram    b2v_inst24(
    .wren_a(ext_wren),
    .rden_a(ext_rden),
    .wren_b(dsp_wren),
    .rden_b(dsp_rden),
    .clock(clk_50m),
    .aclr(resetn),
    .address_a(ext_addr),
    .address_b(dsp_addr),
    .data_a(ext_data),
    .data_b(dsp_data),
    .q_a(ext_data),
    .q_b(dsp_data));

VHDL:

b2v_inst24 : dp_ram
PORT MAP(wren_a => ext_wren,
         rden_a => ext_rden,
         wren_b => dsp_wren,
         rden_b => dsp_rden,
         clock => clk_50m,
         aclr => resetn,
         address_a => ext_addr(12 DOWNTO 0),
         address_b => dsp_addr(12 DOWNTO 0),
         data_a => ext_data(7 DOWNTO 0),
         data_b => dsp_data,
         q_a => ext_data(7 DOWNTO 0),
         q_b => dsp_data);