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bit's avatar
bit
Icon for New Contributor rankNew Contributor
6 years ago

Problem with terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite

Hi! I have a problem with a terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite Edition. I created the hack computer from the Nand To Tetris project on this boar...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Helmut,

RAMs can only be inferred if the read logic is synchronous in the software. I modified the ram16k.vhd and it passed the compilation.

Thanks.

Best regards,

KhaiY