New ContributorProblem with terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite
Hi!
I have a problem with a terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite Edition.
I created the hack computer from the Nand To Tetris project on this board with Quartus Prime Lite Edition version 17.0.0. It was a huge project and a lot of work. In the end everything was fine and I was able to play pong and other games on this system!
When I now load the project with Quartus Prime Lite Edition version 20.1.0, I get the following error in Analysis & Synthesis:
Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete
Analysis and Synthesis.
The problem is obviously the RAM, which is too big. But that was not the case with version 17.0.0!!!
Here is the VHDL of ram16k:
---------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram16k is
port (
clk : in std_logic;
i : in std_logic_vector(15 downto 0);
load : in std_logic;
address : in std_logic_vector(13 downto 0);
o : out std_logic_vector(15 downto 0)
);
end ram16k;
architecture behavior of ram16k is
type ram_t is array(0 to 16383) of std_logic_vector(15 downto 0);
signal ram_s : ram_t := (others =>(others => '0'));
begin
o <= ram_s(to_integer(unsigned(address)));
process (clk)
begin
if (falling_edge(clk) and load = '1') then
ram_s(to_integer(unsigned(address))) <= i;
end if;
end process;
end behavior;
-----------------------------
All Analyses & Synthesis settings are on default. "max_number_of_registers_from_uninferred_rams" is set to -1 (unlimited)!
I am not an FPGA/VHDL expert, I have only build this computer system and have learned during this work a lot about FPGA and VHDL but obviously not enogh to find an explanation for this error. Has anyone an idea what the reason could be?
If anyone is interested to get all VHDLs of this project, please contact me, I provide them under Creative Commons CC BY 4.0
Thank's a lot for help!
