Problem with terasIC DE0-CV borad (Cylone V FPGA) and different versions of the Quartus Prime Lite

Hi Helmut,

The error message in the compilation report is different from the error you shared in this post.

In the compilation report:

Can't read Quartus Prime message file C:/Users/bit/Desktop/Hack Computer/db/Flow Messages are not contained in a QMSG file..

> The software cannot read the content in C:/Users/bit/Desktop/Hack Computer/db/Flow Messages. Kindly check if this file exists and you have the permission to read and write the file

In this forum post:

Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis.

>CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified one or more sets of registers that act as RAM. However, when creating nodes as RAM, Analysis & Synthesis cannot convert all the sets of registers into RAM megafunctions to implement the register logic with M-LAB memory blocks, M4K memory blocks, M9K memory blocks, M-RAM memory blocks, or M144K memory_blocks. As a result, a large number of registers remain in the design, which can cause longer compilation time or result in insufficient memory to complete analysis and synthesis.

ACTION: To avoid problems when processing the design, use coding styles that allow Analysis & Synthesis to infer RAM. Refer to "Recommended HDL Coding Styles," in the Quartus Prime Handbook for examples of coding styles. If the current design already matches one of the suggested coding styles, make sure you turned on the Auto RAM Replacement logic option. You can also replace the logic in the Verilog Design File or VHDL Design File with an explicit instantiation of a RAM megafunction. Otherwise, no action is required.

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified one or more sets of registers that act as RAM. However, Analysis & Synthesis cannot convert the sets of registers into RAM megafunctions because the target device of the current design does not have dedicated RAM hardware. As a result, the registers remain in the design, which can cause longer compilation time or result in insufficient memory to complete Analysis & Synthesis.

ACTION: To avoid problems when processing the design, change the target device to one that has dedicated RAM hardware, or remove the sets of registers that act as RAM from the design. Otherwise, you can set the value of the assignment max_number_of_registers_from_uninferred_rams to a larger value or infinity (-1).

Thanks.

Best regards,

KhaiY