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Altera_Forum
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15 years ago

Problem with SystemVerilog operator ++ in Modelsim

I have some problem simulating code using the SystemVerilog ++ operator. Consider the following example (I tested this on QuartusII Web edition 9.1sp2 using ModelSim AE): --- Quote Start --...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I think cnt1++ is

equivalent to cnt1 = cnt1+1

and not to cnt1 <= cnt1+1

One is immediate the other is a deferred assigment.