Problem with generate

Hi all,

In one of the state of the state machines I was writing, I used generate-endgenerate

for loop to give values of some outputs. But I got the error like:

Error (10170): Verilog HDL syntax error at SystemCU.v(235) near text "generate"; expecting "end"

Error (10170): Verilog HDL syntax error at SystemCU.v(244) near text "endgenerate"; expecting "end"

Could someone help me on this... Thanks in advance.

     STATE_LDR1:
     begin
       PC_BUS=0; ALU_BUS=1; POFF_BUS=0; MDR_BUS=0;
       REG_MUX1=4'b0000; REG_MUX2=4'b0000; REG_MUX3=0;
       ALU_CTR=ALU_NOTHING;
       LD_IR=0; LD_MDR=0; LD_ALU=0;
       Reset_PC=1; LD_PC=0; PC_MUX=0;
       LD_MAR=0; 
       MEM_RW=0; 
     
       LD_REG]=1;
       
       generate
       
       genvar i;
       for(i=0;i<16;i=i+1)
       begin:LDR0_GEN
         if(i!=IR)
         LD_REG=0;
       end
       
       endgenerate
       
       nextstate=STATE_0;
     end