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MDiDo's avatar
MDiDo
Icon for New Contributor rankNew Contributor
6 years ago

Problem with Deinterlacer

Hello, I have a problem with the Deinterlacer IP Core. I created a video system with the following input chain: CVI->CLIPPER->COLOR PLANE SEQUENCER->CHROMA RESAMPLE->DEINTERLACER->MEMORY CONTROLLER-...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I have emailed you a new archive which I further compress the zip. Please let me know if it still cannot get through your email.

Thank you.

  • MDiDo's avatar
    MDiDo
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thank you. I tried your design, but I get always the same problem. I attack the simulation waveforms. As you can see the deinterlacer starts the frame acquisition and sends the control packet with dout_valid (cyan), but after lowes the din_ready (yellow) and stops the frame acquisition. What could be the probem?

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      6 years ago
      Hi, As I tested running the simulation zip shared to you, the simulation seems to run OK as shown in the following screenshot. The din_ready is asserted to backpressure the TPG and then assert again when it is ready to accept data. Please feel free to let me know if you are not seeing the din_ready assert at later stage of your simulation or if you are observing differently. Thank you. [cid:[email protected]] Best regards, Chee Pin
    • MDiDo's avatar
      MDiDo
      Icon for New Contributor rankNew Contributor
      6 years ago

      Sorry I can't see the screenshot. I see "[cid:[email protected]]" , it seems that the image has been not correctly inserted.