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Altera_Forum's avatar
Altera_Forum
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16 years ago

Problem with behavioral code for SR latch

Two behavioral codes for a gated SR latch that to me seem like they should give identical results instead give radically different results, one of which has a glitch that gives wrong behavior (that Quartus warns about). Here is the VHDL for the two cases:

--file mysrlatch1.vhd with incorrect results

library ieee;

use ieee.std_logic_1164.all;

entity mysrlatch1 is port(

r,clk,s,clr:in std_logic;

q: out std_logic);

end mysrlatch1;

architecture arch of mysrlatch1 is

begin

process(r,s,clk,clr) begin

if clr='1' then

q<='0';

elsif clk='1' then

if r='1' then

q<='0';

elsif s='1' then

q<='1';

end if;

end if;

end process;

end arch;

--file mysrlatch2.vhd with correct results

library ieee;

use ieee.std_logic_1164.all;

entity mysrlatch2 is port(

r,clk,s,clr:in std_logic;

q: out std_logic);

end mysrlatch2;

architecture arch of mysrlatch2 is

begin

process(r,s,clk,clr) begin

if clr='1' then

q<='0';

elsif clk='1' and r='1' then

q<='0';

elsif clk='1' and s='1' then

q<='1';

end if;

end process;

end arch;

I see in looking at the code generated for the two cases that case 1 does indeed have a glitch generator with the way it handles the R input. But the two cases seem like they should generate the same results -- the results of running through the process seem like they should be identical. What am I missing? Thanks.

Using Quartus-II version 9.1 build 222, web version. Windows XP home, up-to-date.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    As a general comment, Quartus II, as well as most other FPGA synthesis tools isn't particularly suited to create asynchronous circuits. This has two reasons in my opinion:

    - Most newer FPGAs don't have specific asynchronous register hardware, all latches must be implemented through logic loops

    - Quartus is highly optimized for synchronous circuit performance

    Looking at the VHDL examples, it's not obvious, why they result in rather different logic implementations, as the Quartus RTL Viewer tool reveals. In my opinion, also the mysrlatch2 implementation looks strange. As an additional remark, the latch primitive, that appears in the implementation of mysrlatch1, is replaced in the physical mapping by a logic loop, even with FPGA families that have a physical SR latch (e.g. Cyclone or Stratix). Unfortunately mysrlatch1 has also the flaw of connecting r to both latch inputs, which is analyzed by Quartus as unsafe latch behaviour.

    Finally, I have a third variant, that should be logical equivalent (also reproducing the r versus s priority of both others), that results in another different circuit. 

    library ieee;
use ieee.std_logic_1164.all;
entity mysrlatch3 is port(
r,clk,s,clr:in std_logic;
q: out std_logic);
end mysrlatch3;
architecture arch of mysrlatch3 is
begin
process(r,s,clk,clr) begin
if clr='1' then
q<='0';
elsif clk='1' then
q <= s and not r;
end if;
end process;
end arch;

    Because I know about Quartus' weakness with asynchronous circuits, I would avoid all three and use a synchronous equivalent, if ever possible.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    FvM, thank you very much. I was attempting to get started with behavioral code on "simple stuff", but I guess I inadvertently picked something not so "simple". Maybe that's why the textbooks seem to studiously avoid example SR latches in VHDL?

    I take issue, though, with your third variant -- it will set output q to '0' even when r=s='0' as long as clk is '1' -- so when clk is '1', the memory of q is forgotten, and the circuit does not then function as a gated latch.

    I'm not sure what a "synchronous SR latch" would look like -- the term "latch" generally implies clock level sensitivity, not clock edge sensitivity.

    I'll move on, and keep your comments in mind.

    Also, sorry about not posting the target chip I'm aiming at -- it is a Cyclone-II EP2C35F672C6 FPGA (on a DE-2 board).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Yes, you're right. My third example isn't a valid SR latch.

    You're also right, that a SR-latch is asynchronous by design. So if you exactly need it's behaviour, you have to use asynchronous code. "Use a synchronous equivalent" is dedicated to those cases, where don't need exactly asnchronous behaviour.

    I'm aware of the fact, that asynchronous behaviour is needed in some designs. E.g. to capture a pulse, that is shorter than a system clock period, you can't avoid it. But you can still try to make the remaining part of the logic synchronous, which considerably eases the implementation by the design compiler.