Problem with behavioral code for SR latch

As a general comment, Quartus II, as well as most other FPGA synthesis tools isn't particularly suited to create asynchronous circuits. This has two reasons in my opinion:

- Most newer FPGAs don't have specific asynchronous register hardware, all latches must be implemented through logic loops

- Quartus is highly optimized for synchronous circuit performance

Looking at the VHDL examples, it's not obvious, why they result in rather different logic implementations, as the Quartus RTL Viewer tool reveals. In my opinion, also the mysrlatch2 implementation looks strange. As an additional remark, the latch primitive, that appears in the implementation of mysrlatch1, is replaced in the physical mapping by a logic loop, even with FPGA families that have a physical SR latch (e.g. Cyclone or Stratix). Unfortunately mysrlatch1 has also the flaw of connecting r to both latch inputs, which is analyzed by Quartus as unsafe latch behaviour.

Finally, I have a third variant, that should be logical equivalent (also reproducing the r versus s priority of both others), that results in another different circuit.

library ieee;
use ieee.std_logic_1164.all;
entity mysrlatch3 is port(
r,clk,s,clr:in std_logic;
q: out std_logic);
end mysrlatch3;
architecture arch of mysrlatch3 is
begin
process(r,s,clk,clr) begin
if clr='1' then
q<='0';
elsif clk='1' then
q <= s and not r;
end if;
end process;
end arch;

Because I know about Quartus' weakness with asynchronous circuits, I would avoid all three and use a synchronous equivalent, if ever possible.