Problem with behavioral code for SR latch

FvM, thank you very much. I was attempting to get started with behavioral code on "simple stuff", but I guess I inadvertently picked something not so "simple". Maybe that's why the textbooks seem to studiously avoid example SR latches in VHDL?

I take issue, though, with your third variant -- it will set output q to '0' even when r=s='0' as long as clk is '1' -- so when clk is '1', the memory of q is forgotten, and the circuit does not then function as a gated latch.

I'm not sure what a "synchronous SR latch" would look like -- the term "latch" generally implies clock level sensitivity, not clock edge sensitivity.

I'll move on, and keep your comments in mind.

Also, sorry about not posting the target chip I'm aiming at -- it is a Cyclone-II EP2C35F672C6 FPGA (on a DE-2 board).