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Altera_Forum's avatar
Altera_Forum
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12 years ago

Problem with asynchronous FSM - VHDL

I have a problem with implementation of finite state machine, which is responsible for detection of motor direction based on signals from HALL sensors. The system has three inputs (HALL1, HALL2, HALL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Where is your testbench?

Have you also considered Kaz's comment that most FPGA designs are synchronous guys as that is how FPGAs are designed. You're unlikely to get Async help on this board.

Why have you not used a clock?