Problem with 2 cascaded PLL in CycloneV

Good afternoon,

I'm trying to cascade two PLL's. Every PLL is fractional.

The first PLL gets Clock=75 MHz at its refclk port.

Then, I'm taking the signal from its cascade_out port and connect it to adjpllin port of second PLL.

First PLL gets RESET='0' constant,the second PLL gets RESET from inverted locked port of first PLL.

Unfortunately, nothing happens during simulation -the outputs of second and first PLL are red.

What is wrong with my cascading? Why simulation doesn't work?