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AGofs
Occasional Contributor
Occasional ContributorProblem with 2 cascaded PLL in CycloneV
Good afternoon, I'm trying to cascade two PLL's. Every PLL is fractional. The first PLL gets Clock=75 MHz at its refclk port. Then, I'm taking the signal from its cascade_out port and connect it...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorLet me recreate the issue and will update you , in mean time kindly reset the first PLL for some period of time then try to obtain the data
