Problem witch implementing big automaton

first, remember the counter use is not going to solve your issue much since the associated logic is huge.

--pseudocode
-- divide clk process
process
begin
   wait until clk = '1';
   divideclk <= not divide clk;
end process;
 
then use that divideclk as enable:
process
...clk edge ...etc
if divideclk = '1' then
 
   fail_edge <= '0'; --default
   case count is
       when 0 =>
           if stream = "00101110" then
              count <= 21;
           end if;
       when 1 => 
           if stream = ....
              count <= 102;
              fail-edge <= '1'; --non default
           end if;
 
...etc

I feel this is a case for a memory look-up approach. It looks like you have some 256 states checking a stream of 8bit input data. In stead of using logic we now need about 256 (states) * 256 (input stream) * 8 (next state) bits (or 524288 bits in total) of ram to just code the state machine. If you need to do some actions in some states you will have to add extra memory bits. Now the work will shift from writing case statements to fill the RAM. One disadvantage of using memory blocks is the latency as the next_address is registered inside the memory system. Writing the MIF file will be a lot less tedious then enumerating the 256 or so case statements.

Hi!

here is link to my project: http://rapidshare.com/files/404749014/ahoautomaton.rar

Hi,

I perused the automatTest.vhd file. It truly is a large state machine. I saw 71555 states. If you'd take the approach I suggested earlier you would need more memory bits that you could find in any FPGA: about (2^(17+8) )* 20 = 671 Mbit.